MaddX raises $500M to ship LLM-optimized chips with SRAM+HBM hybrid architecture targeting frontier labs

Summary

MaddX, a chip startup founded by former Google hardware engineers, raised $500M to manufacture LLM-optimized semiconductors. The round was co-led by Main Street and Situational Awareness (Leopold Aschenbrenner's fund), with participation from Jane Street, Spark Capital, NFTG, the Collison brothers (Patrick and John), Andrej Karpathy, and Marvell.

The chip design

MaddX1 combines SRAM and HBM memory in a single chip. CEO Reiner Pope argues this hybrid approach beats either memory type alone. SRAM-only designs like Grock and Cerebras deliver the lowest latency but lack capacity for long-context KV caches. HBM-based chips from Nvidia, Google, and Amazon have capacity but sacrifice latency. MaddX pairs weights in SRAM with HBM for context, which improves HBM utilization and yields better throughput than alternatives. The chip is reticle-scale rather than wafer-scale, avoiding the physical manufacturing risks Cerebras has faced.

Pope designs the chip to prioritize very large matrix operations and systolic array architectures. He argues these specializations will remain relevant across a five-year data center lifecycle. A general-purpose vector unit adds flexibility for non-matrix workloads and costs roughly 5–10% in hardware overhead.

Market positioning

Pope frames CUDA as both Nvidia's moat and constraint. The promise of backward compatibility locks Nvidia into legacy numeric formats, core topologies, and memory architectures designed over a decade ago for general-purpose compute. Frontier labs face extreme cost and wafer supply pressure and are willing to rewrite software for more efficient hardware. CUDA's lock-in dominates the mid-market and tail, where software migration costs are prohibitive. At the head of the market, where frontier models drive demand, hardware efficiency and raw cost per token dominate.

Go-to-market and supply chain

MaddX is targeting frontier labs directly with early customer orders on the scale of gigawatts per year. The fundraise is explicitly tied to ramping supply chain capacity to meet those volumes.

Pope acknowledges the bottleneck problem without resolving it. Logic dies come from TSMC, memory from HBM suppliers, and rack manufacturing faces its own constraints. His strategy is to maximize performance per square millimeter of silicon, betting that as wafer scarcity persists, density becomes the primary lever for cost-per-token improvement. Designing for legacy or lagging-edge process nodes is possible but requires $20–40M per additional node, a bet a startup cannot afford.

Investor signals

Situational Awareness' participation signals that the fund sees frontier AI labs' compute hunger as structural and durably capital-intensive. Jane Street's involvement suggests deep technical scrutiny. Pope notes they are expert technologists who understand what good looks like in custom silicon. The inclusion of the Collison brothers and Karpathy reflects confidence from founders and ML researchers outside the chip industry.